Initially, a typical MPEG image transmission method will be described. By the MPEG method, picture information is transmitted using three types of MPEG image signals comprising I coded data, P coded data, and B coded data. Here, I coded data is an image signal that is coded within one frame and completed within one picture. Image data that is obtained by decoding I coded data is referred to as I picture.
P coded data is an image signal that is obtained by coding a difference with respect to a reference picture that was previously coded to generate I coded data or P coded data. Difference data obtained by decoding P coded data is added to the reference picture, and image data that is obtained by decoding the resultant data is referred to as P picture.
Further, B coded data is an image signal that is obtained by coding differences with respect to two reference pictures that were coded to generate the immediately preceding and immediately following I or P coded data. Difference data that is obtained by decoding B coded data and the reference pictures are added, thereby reproducing image data. This reproduced image data is ref erred to as B picture.
In the MPEG method, the interval between I picture and P picture is not defined. Accordingly, as shown In FIG. 12, it is possible to generate a coded video stream including various intervals between I picture and P picture or intervals between P pictures.
In a coded video stream that is coded by the MPEG method, when I coded data or P coded data is to be decoded, the immediately preceding I or P picture is displayed, while when B coded data is decoded, B picture Is displayed while being decoded.
At the display of I or P picture, decoding of I or P coded data is performed so as to display a picture that was already decoded and stored in an output buffer.
At the display of B picture, decoding of B coded data is performed so as to display B picture that will be decoded.
FIG. 9 illustrates a structure of a conventional image signal reproduction apparatus. The image signal reproduction apparatus as shown in FIG. 9 decodes a coded video stream. A video decoding circuit 9001 decodes an inputted coded video stream 9101.
The decoding is performed in accordance with a decode control signal 9112 that is inputted from a video display control circuit 9007 to the video decoding circuit 9001. Decoded data 9102, 9103, and 9104 are inputted to a first output buffer 9002, a second output buffer 9003, and a third output buffer 9004, respectively. The video decoding circuit 9001 extracts a stream control signal 9111 from the coded video stream 9101 and outputs the extracted signal to the video display control circuit 9007.
The first output buffer 9002 stores the decoded data 9102 outputted from the video decoding circuit 9001, and outputs decoded data 9105 to the video decoding circuit 9001 or a video output circuit 9005. The decoded data 9102 stored in the first output buffer 9002 are I pictures or P pictures.
Similarly, the second output buffer 9003 stores the decoded data 9103 from the video decoding circuit 9001, and outputs decoded data 9106 to the video decoding circuit 9001 or the video output circuit 9005. The decoded data 9103 stored in the second output buffer 9003 are also I pictures or P pictures.
The third output buffer 9004 stores the decoded data 9104 from the video decoding circuit 9001 and outputs decoded data 9107 to the video decoding circuit 9001 or the video output circuit 9005, while the decoded data 9104 stored in the third output buffer 9004 are only B pictures.
In FIG. 9, a sync signal generation circuit 9006 outputs a NTSC sync signal or PAL sync signal 9109. The video display control circuit 9007 outputs the decode control signal 9112 to the video decoding circuit 9001 in accordance with the stream control signal 9111 received from the video decoding circuit 9001 and the sync signal 9109 received from the sync signal generation circuit 9006, and outputs a display control signal 9110 to the video output circuit 9005.
The video output circuit 9005 repeatedly performs an operation of selecting one of the decoded data 9105, 9106, and 9107 from the first output buffer 9002, the second output buffer 9003, and the third output buffer 9004, in accordance with the display control signal 9110 received from the video display control circuit 9007, and outputting the selected data as a video output signal 9108.
FIG. 10 is a flowchart for explaining the control by the video display control circuit 9007. Hereinafter, the data processing procedure by the conventional image signal reproduction apparatus will be described with reference to FIG. 9 and the control flowchart of FIG. 10.
As shown in FIG. 10, in step S10002, the video display control circuit 9007 judges whether a decode starting position of coded data is reached or not on the basis of the stream control signal 9111 from the video decoding circuit 9001, and stands by up to the decode starting position. When the decode starting position is reached, the video display control circuit 9007 performs display setting (step S10003), and then instructs the video decoding circuit 9001 of decoding of coded data (step S10004).
Then, in step S10005, the video display control circuit 9007 judges whether decoding of coded data corresponding to one frame has been completed or not. When the decoding is completed, the circuit 9007 further judges whether all coded data have been decoded or not (step S10006). When decoding of all coded data is not completed, the operation returns to step S10002, while the decoding of all coded data is completed, the control is finished.
FIG. 11(a) shows an input pattern of a coded video stream. FIG. 11(b) shows decoded data stored in the first output buffer 9002, the second output buffer 9003 and the third output buffer 9004, and the video output signal 9108, in the case where the coded video stream has the input pattern as shown in FIG. 11(a).
In FIG. 11, for example, P8 coded data is decoded and stored in the second output buffer 9003 prior to B6 and B7 coded data, and B6 and B7 coded data are thereafter decoded and stored in the third output buffer 9004. In the video output signal 9108, however, B6 and B7 pictures are located forward of P8 picture.
High-speed reproduction for arbitrary coded video streams, which is confined to double-speed reproduction is implemented in Japanese Published Patent Application No. 2000-165818.
This conventional image signal reproduction can achieve high-speed reproduction by controlling the reproduction speed of images. However, at the high-speed reproduction, only I and P coded data are decoded while all B coded data are skipped. Therefore, when the coded data are arranged according to the input pattern of the coded video stream as shown in FIG. 12, the interval between I picture and P picture and the interval between P pictures in the decoded video output are not uniform. More specifically, the intervals are four pictures, two pictures, three pictures, one picture, and three pictures as shown in FIG. 12, whereby the reproduction speed is not constant.
Further, in the case of a coded video stream that does not include B pictures, no picture is skipped, whereby high-speed reproduction cannot be realized.